The present invention relates to the testing of through silicon vias in semiconductor structures and, more particularly, to the testing of through silicon vias by an apparatus that may test each through silicon via before the semiconductor structure is complete.
Three-dimensional (3D) stacking of semiconductor chips promises higher transistor densities and smaller footprints of electronic products. 3D stacking is a single package containing a vertical stack of semiconductor chips which are interconnected by means of through silicon vias (TSVs). 3D stacking based on TSVs offers the benefits of more functionality, higher bandwidth and performance at smaller sizes, alongside lower power consumption and cost, even in an era in which conventional feature-size scaling becomes increasingly difficult and expensive. TSVs provide an electrical connection from the active front-side (face) of a semiconductor chip through the semiconductor substrate to the back-side of the substrate. TSVs allow a semiconductor chip or wafer to be vertically interconnected to another semiconductor chip or wafer. TSVs also allow the interconnection of multiple vertically stacked semiconductor chips or wafers with each other.
3D stacks of semiconductor chips interconnected by TSVs need to be tested for manufacturing defects, in order to guarantee sufficient outgoing product quality to a customer. Current leakage associated with TSVs is a significant reliability concern in semiconductor structures containing TSVs. In the present state of the art, additional processing must be completed to enable direct probing of structures directly contacting the TSVs (or TSV capture pads corresponding to the TSVs) to test for current leakage. The TSVs and surrounding protection may actually be damaged by direct probing. To prevent damage to the TSVs, leakage measurements may only be done in the kerf structures, not on the actual product, which limits the number of TSVs to be tested to a small sample of the total number of TSVs present in a chip. Additionally, only a single threshold for detection of leakage may exist meaning only a binary classification of leakage is used. Such a binary classification of current leakage may not be adequate for accurately assessing any shift in TSV leakage current with respect to time.